Shame on you! We are not talking about the criminal trial of a former president nor the situation in the Middle East. The subject is the Bias setting on your IRF510 amplifier circuit.
Pout in dB and Bias level from 3 to 4.3VDC
Above is a representative typical IRF510 Linear amplifier circuit which of course is shown in LT Spice. V1 is the normal supply voltage at 12VDC and V2 is the Bias Voltage shown as 3VDC and V3 is the driver signal from prior stages shown at 5v.
This is a really interesting circuit to simulate as you soon see that many of the component values if changed, do little to affect what is coming out of the pipeline. BUT one or two of the components have a significant impact as even a small change will dramatically affect the output.
Now up front the 3VDC Bias is way too low but we need to start with that to see how the BIAS is a major player. At 3VDC, the output is less than the input.
We hardly hit 0 dB at 30 MHz. So that is not a good set point!
We have now upped the bias to 3.6VDC and still nothing has changed much.
Now the Bias is set to 3.7VDC and look what happened.
But at the peak that is only 3.5dB of gain and of note you see why the IRF510 IN THIS CIRCUIT starts to poop out beyond 40M.
So lets juice things up to 3.9VDC.
At the 3.9VDC level the high point is about 28dB and at 20M it drops down to about 18.5dB. So it is amplifying but a huge drop between 80 and 20M.
One more look at 4.2VDC on the bias. At the peak is 36dB and at 20M 24dB.
So let us see a plot at 4.2VDC along with the input voltage. The Green is the output and the blue the input. The delta spacing between the two lines is almost exact so that the amp is linearly replicating the input. One issue is a droopy input and so a constant input would improve the output.
In true engineering fashion I made a plot (above) of the Bias levels from 3 to 4.3VDC and using LT Spice plotted the expected output from the IRF510. The plot measurements were taken at 16MHz so to represent what you would see somewhere between 14 and 18MHz.
What does this say to us? Graphically we can see that for a range of values from 3 to 3.6 VDC -- not much happening. But once you hit 3.7VDC there is a jump in output. From the 3.7 to 4VDC is the greatest increase in output. From there to 4.3VDC we see what looks like gain compression (smaller levels of gain increase for an incremental increase in Bias).
Noteworthy is this is a pencil and paper exercise, well OK a computer simulation, with no soldering involved. The next step would be to build the circuit and run a test at 16MHz to compare actuals with the simulation. But the real value is to highlight the potential impact of the Bias setting as it drives the output level.
In a quick look see, likely an optimal setting would be to fix the Bias at 3.95VDC. The other factor not calculated would be the idling current as the Bias levels to give that highest level of output would make the IRF510 "Smoking Hot" and sure to burn its outline on your thumb as you do the thumb temperature test.
An important note that appears on the LT Spice schematic and that is the LT Spice Directive k L1 L2 1. You can see that just above L1 and L2 in the schematic. The L1 and L2 windings (8 turns bifilar on a FT-37-43 core) are twisted with about 8 twists to the inch using two colors of #26 wire. Note the phasing dots and the wiring is such that the start of the second turn is connected to the end of the 1st turn and that combo is connected to the Drain of the IRF51o. The Spice Directive spells out that the inductors are closely coupled, and that factor is 1 (the highest level).
Some notes -- 8 Turns per winding (L1, L2) is actually 22.4uH as I know someone will check that and because of the way it is connected, regardless of the number of turns it is a 4:1 step up transformation.
I encourage you use LT Spice and test drive the circuit and purposefully leave off the k L1 L2 1 directive -- the output drops off the cliff like a heavy rock. Care in building Ferrite Core transformers is critical to optimal performance. Scramble winding cores for a HB Double Balanced Mixer is another example of where that is the wrong answer!
I can see that a better circuit maybe required and that the Bias Level is critical -- 1/10 of a volt changes the circuitry from a power sink to a power amp.
Undoubtedly there will be blog readers who do not agree with this post. But critical to my argument is that the simulations are pointing to the significant impact of the bias level and the circuit constants. Noted: No soldering needed, and the Nano VNA is OFF.
Where is your Bias set?
73's
Pete N6QW